JobRewards - Aemulus Corporation Sdn Bhd

Aemulus Corporation Sdn Bhd

Junior R&D Digital Design Engineer

Job Type:  Full Time

Location: Bayan Lepas, Pulau Pinang

Experiences: Entry Level +

Salary (MYR): 3,000 – 5,000

Job Description:

  • Design & Coding in Verilog/VHDL.
  • Generate new ideas and way of work.
  • Work smart, support colleagues, and celebrate together.
  • Visualize the multi-parallel pipe-lining operations of a FPGA.

Key Skills and Experiences:

  • Candidates who love to work with FPGA.
  • Candidates who think they can achieve much more in their career with their undiscovered talents
  • Candidates who feel that their growth are saturated by their monotonous job day in day out.
  • Fresh/Junior/Senior positions are available.
  • Candidates should be Malaysian Citizens.

Apply Now

JobRewards scroll up icon